1. Field
The following description relates to an isolation structure, a semiconductor with an isolation structure, a method for fabricating an isolation structure, and for example, to an isolation structure of a semiconductor device containing a deep trench isolation (DTI) structure, and a fabrication method thereof.
2. Description of the Related Art
Along with the recent advancement in electronic engineering, demands for compact-sized multi-functional electronic apparatuses have greatly increased. A system on chip (SoC) is one of the technologies that were developed to meet such increasing demands. The SoC technology refers to implementing a system that integrates a plurality of devices into a single chip.
Due to the recent development and introduction of Micro-Electro-Mechanical Systems (MEMS) or Nano-Electro-Mechanical Systems (NEMS) technology, the attempts to implement various devices on a single chip have increased.
However, one problem posed by such technologies is that the possibility of having interference between two or more devices increases when a plurality of devices is integrated on one substrate. For example, when electric interference is generated, the electric interference may affect the operation of other devices on the substrate, possibly causing various malfunctions in the devices.
In order to prevent the above-mentioned problems, conventionally, a device isolation structure that electrically isolates the devices on a substrate is fabricated.
Trench isolation is a common technique for forming a device isolation structure. In trench isolation technique, a trench is formed to a predetermined depth of a silicon substrate, an oxide layer is buried in the trench, and by chemical mechanical polishing, unnecessary portion of the oxide layer is removed, leaving a device isolation structure within the silicon substrate.
However, the conventional trench isolation method has a shortcoming. That is, in forming a deep trench using polishing process, etch damage is done to the semiconductor substrate and defect areas are also formed on the surface of the substrate. These damages or defects cause a leakage of electric current between the devices within the semiconductor.
FIG. 1 includes electron microscope images obtained in a physical analysis of a semiconductor device fabricated according to a conventional technique. As illustrated in the first microscope image found in FIG. 1, defects are generated on the surface of a substrate of a semiconductor device.
Further, the deep trench isolation (DTI) structure that is formed adjacent to a device receiving high bias exhibits an increase in leak electric current as it is difficult to design the appropriate thickness or processing conditions.
Additionally, the use of a conventional technique for fabricating device isolation involves a high risk of causing physical defects such as voids in the semiconductor device, for example, during the process of filling the interior of a deep trench.